+48V Quad Hot-Swap Controllers For
Power-Over-LAN
14 ______________________________________________________________________________________
Internally the circuit compares the output voltage with
V
CC
to determine when the FET is completely on. A
POK condition is met when:
(V
CC
- V
OUT
) d 1.5V
The internal circuit monitors V
OUT
to determine the
value of the foldback current when the circuit goes into
current-limit conditions. The value of the current limit
decreases as the output voltage decreases in order to
limit the power dissipation of the FET. The nonlinear
relationship between V
OUT
and I
LIM
is depicted in
Figure 8.
The foldback circuit is active whenever the MAX5913A/
MAX5914A are in current-limit mode after an overcur-
rent condition has been detected.
Connect a catch diode to analog ground and a 100&
resistor in series with OUT_ to limit the current during
negative inductive kicks that can bring OUT_ below the
ground potential (Figure 5).
Relay Drivers
The MAX5913A/MAX5914A include on-chip relay drivers,
RYLD_, capable of sinking 100mA. When RLYON_ goes
high, the MAX5913A/MAX5914A immediately enable the
relay driver, and the corresponding ON_ switch control
input is delayed 25.6ms to allow the relay to close under
a zero-voltage condition. When RLYON_ goes low, the
MAX5913A/MAX5914A immediately turn off the corre-
sponding switch, and then turn off the relay driver after a
3.2ms delay, ensuring the relay contacts open under a
zero-current condition. The polarity of the MAX5913A
FOLDBACK
NL CONTROL
FROM LOGIC
CONTROLLER
DRAIN
R
SENSE
GATE
TO LOGIC
CONTROLLER
CSP
10礎
8礎
1mA
OUT
OCEN
ON
AGND
DGND
RLYON
RLYD
V
RLY
V
CC
CHARGE PUMP
POK COMPARATOR
DELAY
DUAL LEVEL
DETECTION
1mA
V
DD
1.236V
UVLO
RTIM
DC
RTRYEN
OPEN-CIRCUIT
DETECTOR
DC COUNTER
RESET LOGIC
RELAY
CONTROL
TIMING
OSCILLATOR
LOGIC
CONTROLLER
CSP -1.5V
3mV
142.5mV
420mV
V
DD
DGND
MAX5913A
MAX5914A
Figure 6. Functional Diagram
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